1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for improving the operation of a new microprocessor adapted to execute programs designed for a processor having an instruction set different than the instruction set of the new microprocessor.
2. History of the Prior Art
Recently, a new microprocessor was developed which combines a simple but fast host processor (called “morph host”) and software (called “code morphing software”) to execute application programs designed for a processor (the target processor) different than the morph host processor. The morph host processor executes the code morphing software to translate the application programs into morph host processor instructions which accomplish the purpose of the original target software. As the target instructions are translated, the new host instructions are both executed and stored in a translation buffer where they may be accessed without further translation. Although the initial translation and execution of a program is slow, once translated, many of the steps normally required to execute a program in hardware are eliminated. The new microprocessor has demonstrated that a simple fast processor designed to expend little power is able to execute translated “target” instructions at a rate equivalent to that of the “target” processor for which the programs were designed.
In order to be able to execute programs designed for other processors at a rapid rate, the morph host processor includes a number of hardware enhancements. One of these enhancements is a gated store buffer which resides between the host processor and the translation buffer. A second enhancement is a set of host registers which store state of the target machine at the beginning of any sequence of target instructions being translated. Generated as sequences of morph host instructions are executed and memory stores are placed in the gated store buffer. If the morph host instructions execute without raising an exception, the target state at the beginning of the sequence of instructions is updated to the target state at the point at which the sequence completed and the memory stores are committed to memory.
If an exception occurs during the execution of the sequence of host instructions which have been translated, processing stops; and the entire operation may be returned or rolled back to the beginning of the sequence of target instructions at which known state of the target machine exists in the set of host registers. This allows rapid and accurate handling of exceptions.
The combination of the code morphing software and the enhanced host processing hardware dynamically translates sequences of target instructions into sequences of instructions of a host instruction set which may be reused without being translated again. Moreover, the new processor also optimizes the translated instructions during and after the initial translation. For example, sequences of host instructions translated from the target program may be reordered, rescheduled, and optimized in other manners to provide code which executes rapidly. Optimized sequences of translated instructions may often be linked with other translated and optimized sequences of instructions so that the process may further optimized as the instructions continue to be executed. The new processor is described in detail in U.S. Pat. No. 5,832,205, Improved Memory Control System For Microprocessor, issued Nov. 3, 1998, to E. Kelly et al., and assigned to the assignee of the present invention.
One difficulty which has limited the speed of operation of the improved microprocessor has been that many instructions being translated and stored for reuse are reused only infrequently if at all. Because the translation process is time consuming, the average time for execution of all translated instructions is lowered by translating these little used instructions. This is especially a problem where the translated sequences have been linked to other translated sequences and significantly optimized.
In addition to the time taken to translate and optimize sequences of instructions, each translation requires storage. If each translated sequence continues to be stored in the translation buffer, an inordinate amount of storage is ultimately required.
It is desirable to increase the speed of execution of instructions by the new microprocessor while reducing the storage required for translated instructions.